1. Field of the Invention
The present invention relates to circuit substrates and semiconductor devices, and particularly to a circuit substrate to which a semiconductor element is to be flip-chip connected in a face-down structure and a semiconductor device in which the semiconductor element is flip-chip connected in the face-down structure to the circuit substrate.
2. Description of the Related Art
When a semiconductor element is mounted to a circuit substrate to make a semiconductor device, the semiconductor element may be flip-chip mounted to the circuit substrate in a face-down configuration, in which a main surface of the semiconductor element faces the circuit substrate, as one semiconductor-element mounting structure.
To implement this structure, a method (disclosed, for example, in Japanese Unexamined Patent Application Publication No. 9-97816) is used in which a load is applied to the semiconductor element, having bumps, toward the circuit substrate, having mounting pads, with an adhesive disposed therebetween to align the bumps with the mounting pads to make the bumps into contact with the mounting pads; and the adhesive is cured by heat while the bumps and mounting pads are contacting, to secure the semiconductor element to the circuit substrate to make the semiconductor device.
In the semiconductor device, manufactured by this method, the semiconductor element is secured to the circuit substrate with the adhesive supplied therebetween, and a state is maintained in which the bumps of the semiconductor element is pressed against the mounting pads of the circuit substrate. As a result, the mechanical contacts of the bumps and mounting pads are maintained, and their electrical contacts are also obtained and maintained.
In some cases, solid patterns are disposed in addition to wiring patterns and the mounting pads at an area (hereinafter called an element mounting area) where the semiconductor element is mounted to the circuit substrate (for example, see Japanese Unexamined Patent Application Publication No. 2003-338666).
It has been disclosed that placing such solid patterns increases the rigidity of the circuit substrate and improves the reliability of the semiconductor device; and in addition, plating the surfaces of the solid patterns with nickel (Ni) and gold (Au) increases the rigidity of the solid patterns, thus further improving the rigidity of the circuit substrate.
It has been also proposed that wiring patterns and dummy patterns are disposed at the element mounting area in the circuit substrate to eliminate non-uniformity of the density of patterns to prevent warping of the circuit substrate caused by a difference in thermal expansion coefficients (for example, in Japanese Unexamined Patent Application Publication No. 2006-32872).
In the above-described related-art cases, the wiring patterns and dummy patterns are plated with gold (Au) to increase corrosion resistance. However, since a gold (Au) plating layer has low contact performance with adhesives, a sufficient contact force is not obtained. Therefore, it is difficult to maintain the contacts between wiring patterns and connection terminals of the semiconductor element. To solve this problem, in the related-art cases, the dummy patterns have branch shapes to form small protrusions, that is, a plurality of indentations and projections, to increase the contact force by an anchor effect.
As described above, generally, a low contact force is provided between metals such as gold (Au) and adhesives. Therefore, delaminating is likely to occur at the interface between an adhesive and the gold (Au) plating layers disposed over the surfaces of the dummy patterns and solid patterns, after mounting.
As a result, it is difficult to maintain a state in which the bumps of the semiconductor element is pressed against the mounting pads of the circuit substrate, and satisfactory electrical connections are not maintained therebetween. Especially when the semiconductor device is left in an environment of a high temperature and a high humidity, delaminating further advances and desired reliability is not obtained.
One method can be considered in which insulating resin layers, which have high contact performance with adhesives, are disposed over the dummy patterns (solid patterns). When the dummy patterns (solid patterns) have a large area at the element mounting area, the insulating resin layers also have a large area.
Having a large area, the insulating resin layers have a large elastic recovery force. Therefore, when the semiconductor element is mounted to the circuit substrate, if there are insulating resin layers having a large area at the element mounting area, the elastic recovery force of the insulating resin layers exceeds a bonding load even if the bonding load is applied to the semiconductor element, making the connections between the bumps of the semiconductor element and the mounting pads of the circuit substrate unstable.
If an increased load is applied to the semiconductor element to make the bonding process reliable, internal wiring or circuit elements at portions where the bumps are formed in the semiconductor element may be damaged.